1. Field of the Invention
This invention relates to a nonvolatile memory circuit formed in a semiconductor integrated circuit device, and more particularly to a nonvolatile memory circuit device having a sense amplifier for detecting memory data based on a difference between currents flowing through a dummy cell and a memory cell from which memory data is read out so as to perform a stable circuit operation in a wide range of power source voltage level. 2. Description of the Related Art
Conventionally, the readout circuit of the nonvolatile memory circuit device is constituted as shown in FIG. 1, for example. Comparator 1 acting as a sense amplifier detects memory data by comparing reference potential Vref with readout signal potential Vin from a selected one of memory cells 4 in memory cell array 6 and outputs signal Dout corresponding to the memory data. Reference potential Vref is generated from reference potential generating circuit 2 and supplied to one input terminal of comparator 1. Intermediate potential generating circuit 3 generates intermediate potential V.sub.DD between power source potentials Vcc and Vss. Reference potential Vref is set to be slightly lower than potential V.sub.DD. In the miniaturized memory cell, the memory cell may be damaged or erroneous programming operation will be effected if power source voltage Vcc is applied to the drain as it is in the data readout mode. In order to solve this problem, intermediate potential generating circuit 3 is used to suppress the drain potential to a minimum in the data readout mode. The output terminal of intermediate potential generating circuit 3 is connected to one end of the current path of each column selection transistor 5 and to the other input terminal of comparator 1. The other end of the current path of each column selection transistor 5 is connected to a corresponding one of bit lines BL. The gate of each column selection transistor 5 is supplied with column selection signal CSS from a column decoder (not shown). Word lines WL are arranged to intersect bit lines BL. Memory cells 4 each formed of a transistor of floating gate structure are disposed on the intersection of word lines WL and bit lines BL and arranged in a matrix form. The drain of each memory cell 4 is connected to bit line BL, the source thereof is connected to ground terminal Vss and the control gate thereof is connected to word line WL. Each word line WL is supplied with row selection signal RSS from a row decoder (not shown). Memory cell 4 of memory cell array 6 is selected based on column selection signal CSS and row selection signal RSS. The readout data from a selected one of memory cells 4 is supplied to the other input terminal of comparator 1 via bit line BL and the current path of column selection transistor 5. In the data readout mode, the drain of memory cell 4 is applied with potential V.sub.DD lower than power source potential Vcc from intermediate potential generating circuit 3. As a result, the potential amplitude of the readout data becomes smaller than in the case where power source potential Vcc is applied, and it is supplied to comparator 1 as readout signal potential Vin from memory cell 4.
However, since there are provided many analog circuits such as comparator 1, reference potential generating circuit 2 and intermediate potential generating circuit 3 in the circuit of FIG. 1, the range of the operation power source voltage level is narrow and the power consumption becomes large. In particular, since the potential amplitude of an input voltage applied to the other input terminal of comparator 1 is limited by intermediate potential generating circuit 3, it becomes necessary to constitute comparator 1 in the complex construction which is inherent to an analog circuit. With such a sense amplifier, the range of the operation power source voltage level is narrow, it is difficult to operate the sense amplifier at a low voltage and the power consumption becomes large.